|Active pixels H x V||1608 x 1104|
|Resolution (MP)||1.7 MP|
|Optical format||17.55 (1.1”)|
|Active pixels (H x V)||9.0 μm|
|Frame rate (FPS)||660 FPS|
|Dynamic Range 10bit/12bit||86 dB|
SPINOSAURUS EVO is a highly customizable and user-programmable FPGA based on high-speed smart cameras, is a high-end FPGA camera with a Xilinx Zynq FPGA and high-speed imaging sensor and a 10 Gigabit Ethernet. It includes highperformance ARM System-on-Chip (SoC) technology combined with a turbocharged industrial SONY imaging sensor.
With high-performance FPGA System-on-Chip (SoC) technology, the Spinosaurus EVO camera family opens new dimensions in computer vision. It is a global shutter industrial camera with high frame rates and an open FPGA architecture. With FPGA processing power the image processing algorithms can run in real-time on the camera. Just add your imagination.
Spinosaurus EVO includes full customizable and user-programmable open reference design for a high-speed, FPGA-based camera and application development system. Its emphasis is on an open hardware/software development model, high-frame rates, real-time image processing on FPGA and modern graphical user interface support on the PC side. A suite of versatile and high-performance tools for Xilinx Zynq Ultrascale+ SoC FPGA are available to develop algorithms and process data in real-time. Images are acquired by SONY PREGIUS GEN3 sensors with a SLVS-EC v1.2 interface (8x 2.3 Gbps) achieving a brilliant image at very high speed. The on-board 4GB LPDDR4 memory with 9.6 GB/s of bandwidth enables usage of complex buffered image processing. The reference design can be easily edited with standard Xilinx Vivado tools. OptoMotive´s custom IP cores seamlessly integrate inside the Xilinx Vivado toolchain. A large portion of FPGA (PL) is free for the programming and development of new algorithms or the implementation of additional IP cores. The 1.2 GHz Dual Core ARM Cortex A53 Programmable Subsystem runs a Linux OS with custommade EVO control and streaming stack (including Zero-copy TCP/IP stack). The SoC also includes dual 600MHz Cortex R5 processors which are free for user data processing. User applications or custom data post-processing can be easily added to any existing design.