Specific IP cores can be integrated into FPGAs on or cameras.
AXIS_RLE is an image compression IP core which cuts off background of image and encodes the rest of the image by counting length of equal pixels. The input and output signals are 64-bit wide and carry information of 8 parallel pixels.
Image pixels are sorted into 3 categories:
- RLE Encoding of pixels below the threshold: Any pixels whose value is found to be below the programmable threshold will be encoded by a value of ‘0’, followed by a 16 bit little-endian value indicating the number of ‘below-threshold’ values in the run.
- RLE Encoding of pixels equal to 255: Any pixels whose value is found to be equal to ‘255’ are encoded as an ‘0xFF’ value followed by an 8 bit little-endian value indicating the number of ‘255’ values in the run.
- Pixels values passed to the host unchanged: Any pixels whose value is equal to or greater than the threshold, up to and including the value of 254 are left unaltered and passed down to the host intact.